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features description applications ads5232 sbas294a ? june 2004 ? revised march 2006 dual, 12-bit, 65msps, +3.3v analog-to-digital converter single +3.3v supply the ads5232 is a dual, high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter high snr: 70.7dbfs at f in = 5mhz (adc). this converter includes a high-bandwidth total power dissipation: sample-and-hold amplifier that gives excellent internal reference: 371mw spurious performance up to and beyond the nyquist external reference: 335mw rate. the differential nature of the sample-and-hold internal or external reference amplifier and adc circuitry minimizes even-order harmonics and gives excellent common-mode noise low dnl: 0.3lsb immunity. flexible input range: 1.5v pp to 2v pp the ads5232 provides for setting the full-scale range tqfp-64 package of the converter without any external reference circuitry. the internal reference can be disabled, allowing low-drive, external references to be used for communications if processing improved tracking in multichannel systems. communications base stations the ads5232 provides an over-range indicator flag test equipment to indicate an input signal that exceeds the full-scale medical imaging input range of the converter. this flag can be used to video digitizing reduce the gain of front-end gain control circuitry. there is also an output enable pin to allow for ccd digitizing multiplexing and testing on a pc board. the ads5232 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. the ads5232 is available in a tqfp-64 package. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2004?2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
12-bit pipelined adc error correction logic timing/duty cycle adjust (pll) internal reference 3-state output s/h d11a d0a 12-bit pipelined adc error correction logic 3-state output s/h d11b d0b a v d d oe a v d r v sda t a sen sclk sel ovr a ovr b in a cm in a int/ ext clk dv a dv b ref t refb in b v i n oe b stpd in b ads5232 v i n serial interface disable_pll
absolute maximum ratings (1) ads5232 sbas294a ? june 2004 ? revised march 2006 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) specified package temperature package ordering transport product package-lead designator range marking number media, quantity ads5232ipag tray, 160 ads5232 tqfp-64 pag ?40c to +85c ads5232ipag ads5232ipagt tape and reel, 250 (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the ti website at www.ti.com . over operating free-air temperature range (unless otherwise noted) supply voltage range, avdd ?0.3v to +3.8v supply voltage range, vdrv ?0.3v to +3.8v voltage between avdd and vdrv ?0.3v to +0.3v voltage applied to external ref pins ?0.3v to +2.4v analog input pins (2) ?0.3v to min [3.3v, (avdd + 0.3v)] case temperature +100c operating free-air temperature range, t a ?40c to +85c lead temperature +260c junction temperature +105c storage temperature ?65c +150c (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. (2) the dc voltage applied on the input pins should not go below ?0.3v. also, the dc voltage should be limited to the lower of either 3.3v or (avdd + 0.3v). if the input can go higher than +3.3v, then a resistor greater than or equal to 25 w should be added in series with each of the input pins. also, the duty cycle of the overshoot beyond +3.3v should be limited. the overshoot duty cycle can be defined either as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. for a peak voltage between +3.3v and +3.5v, a duty cycle up to 10% is acceptable. for a peak voltage between +3.5v and +3.7v, the overshoot duty cycle should not exceed 1%. any overshoot beyond +3.7v should be restricted to less than 0.1% duty cycle, and never exceed +3.9v. 2 submit documentation feedback www .ti.com
recommended operating conditions ads5232 sbas294a ? june 2004 ? revised march 2006 ads5232 min typ max units supplies and references analog supply voltage, avdd 3.0 3.3 3.6 v output driver supply voltage, vdrv 3.0 3.3 3.6 v ref t ? external reference mode 1.875 2.0 2.05 v ref b ? external reference mode 0.95 1.0 1.125 v refcm = (ref t + ref b )/2 ? external reference mode (1) v cm 50mv v reference = (ref t ? ref b ) ? external reference mode 0.75 1.0 1.1 v analog input common-mode range (1) v cm 50mv v clock input and outputs adclk input sample rate pll enabled (default) 20 65 msps pll disabled 2 30 (2) msps adclk duty cycle pll enabled (default) 45 55 msps low-level voltage clock input 0.6 v high-level voltage clock input 2.2 v operating free-air temperature, t a ?40 +85 c thermal characteristics: q ja 42.8 c/w q jc 18.7 c/w (1) these voltages need to be set to 1.5v 50mv if they are derived independent of v cm . (2) when the pll is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. a 45%?55% duty cycle variation is acceptable up to a frequency of 30msps. if the device needs to be operated in the pll disabled mode beyond 30msps, then the duty cycle needs to be maintained within 48%?52% duty cycle. 3 submit documentation feedback www .ti.com
electrical characteristics ads5232 sbas294a ? june 2004 ? revised march 2006 t min = ?40c and t max = +85c. typical values are at t a = +25c, clock frequency = 65msps, 50% clock duty cycle, avdd = 3.3v, vdrv = 3.3v, transformer-coupled inputs, ?1dbfs, i set = 56.2k w , and internal voltage reference, unless otherwise noted. ads5232 parameter test conditions min typ max units dc accuracy no missing codes tested dnl differential nonlinearity f in = 5mhz ?0.9 0.3 +0.9 lsb inl integral nonlinearity f in = 5mhz ?2.5 0.4 +2.5 lsb offset error (1) ?0.75 0.2 +0.75 %fs offset temperature coefficient (2) 6 ppm/c fixed attenuation in channel (3) 1 %fs fixed attenuation matching across channels 0.01 0.2 db gain error/reference error (4) ?3.5 1.0 +3.5 % fs gain error temperature coefficient 40 ppm/c power requirements (5) internal reference power dissipation (5) analog only (avdd) 260 297 mw output driver (vdrv) 111 142 mw total power dissipation 371 439 mw external reference power dissipation analog only (avdd) 224 mw output driver (vdrv) 111 mw total power dissipation 335 mw vref t 1.875 2 2.05 mw vref b 0.95 1 1.125 mw total power-down 88 mw reference voltages vref t reference top (internal) 1.9 2.0 2.1 v vref b reference bottom (internal) 0.9 1.0 1.1 v v cm common-mode voltage 1.4 1.5 1.6 v v cm output current (6) 50mv change in voltage 2 ma vref t reference top (external) 1.875 v vref b reference bottom (external) 1.125 v external reference common-mode v cm 50mv v external reference input current (7) 1.0 ma (1) offset error is the deviation of the average code from mid-code with ?1dbfs sinusoid from ideal mid-code (2048). offset error is expressed in terms of % of full-scale. (2) if the offset at temperatures t 1 and t 2 are o 1 and o 2 , respectively (where o 1 and o 2 are measured in lsbs), the offset temperature coefficient in ppm/c is calculated as (o 1 ? o 2 )/(t 1 ? t 2 ) 1e6/4096. (3) fixed attenuation in the channel arises because of a fixed attenuation in the sample-and-hold amplifier. when the differential voltage at the analog input pins is changed from ?v ref to +v ref , the swing of the output code is expected to deviate from the full-scale code (4096lsb) by the extent of this fixed attenuation. note: v ref is defined as (ref t ? ref b ). (4) the reference voltages are trimmed at production so that (vref t ? vref b ) is within 35mv of the ideal value of 1v. this specification does not include fixed attenuation. (5) supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3v. (6) the v cm output current specified is the drive of the v cm buffer if loaded externally. (7) average current drawn from the reference pins in the external reference mode. 4 submit documentation feedback www .ti.com
ads5232 sbas294a ? june 2004 ? revised march 2006 electrical characteristics (continued) t min = ?40c and t max = +85c. typical values are at t a = +25c, clock frequency = 65msps, 50% clock duty cycle, avdd = 3.3v, vdrv = 3.3v, transformer-coupled inputs, ?1dbfs, i set = 56.2k w , and internal voltage reference, unless otherwise noted. ads5232 parameter test conditions min typ max units analog input differential input capacitance 3 pf analog input common-mode range v cm 0.05 v differential input voltage range internal reference 2.02 v pp external reference 2.02 (vref t ? vref b ) v pp voltage overload recovery time (8) 3 clk cycles ?3dbfs input, 25 w series input bandwidth 300 mhz resistance digital data inputs logic family +3v cmos compatible v ih high-level input voltage v in = 3.3v 2.2 v v il low-level input voltage v in = 3.3v 0.6 v c in input capacitance 3 pf digital outputs data format straight offset binary (9) logic family cmos logic coding straight offset binary or btc low output voltage (i ol = 50a) +0.4 v high output voltage (i oh = 50a) +2.4 v 3-state enable time 2 clocks 3-state disable time 2 clocks output capacitance 3 pf serial interface sclk serial clock input frequency 20 mhz conversion characteristics sample rate 20 65 msps data latency 6 clk cycles (8) a differential on/off pulse is applied to the adc input. the differential amplitude of the pulse in its on (high) state is twice the full-scale range of the adc, while the differential amplitude of the pulse in its off (low) state is zero. the overload recovery time of the adc is measured as the time required by the adc output code to settle within 1% of full-scale, as measured from its mid-code value when the pulse is switched from on (high) to off (low). (9) option for binary two?s complement output. 5 submit documentation feedback www .ti.com
ac characteristics ads5232 sbas294a ? june 2004 ? revised march 2006 t min = ?40c and t max = +85c. typical values are at t a = +25c, clock frequency = maximum specified, 50% clock duty cycle, avdd = 3.3v, vdrv = 3.3v, ?1dbfs, i set = 56.2k w , and internal voltage reference, unless otherwise noted. ads5242 parameter conditions min typ max units dynamic characteristics f in = 5mhz 75 86 dbc sfdr spurious-free dynamic range f in = 32.5mhz 85 dbc f in = 70mhz 83 dbc f in = 5mhz 82 92 dbc hd 2 2nd-order harmonic distortion f in = 32.5mhz 87 dbc f in = 70mhz 85 dbc f in = 5mhz 75 86 dbc hd 3 3rd-order harmonic distortion f in = 32.5mhz 85 dbc f in = 70mhz 83 dbc f in = 5mhz 68 70.7 dbfs snr signal-to-noise ratio f in = 32.5mhz 69.5 dbfs f in = 70mhz 67.5 dbfs f in = 5mhz 67.5 70.3 dbfs sinad signal-to-noise and distortion f in = 32.5mhz 69 dbfs f in = 70mhz 67 dbfs 5mhz full-scale signal applied to 1 channel; crosstalk ?85 dbc measurement taken on the channel with no input signal f 1 = 4mhz at ?7dbfs two-tone, third-order imd3 90.9 dbfs intermodulation distortion f 2 = 5mhz at ?7dbfs 6 submit documentation feedback www .ti.com
timing characteristics (1) ads5232 sbas294a ? june 2004 ? revised march 2006 timing diagram typical values at t a = +25c, avdd = vdrv = 3.3v, sampling rate and pll state are as indicated, input clock at 50% duty cycle, and total capacitive loading = 10pf, unless otherwise noted. parameter min typ max units 65msps with pll on t a aperture delay 2.1 ns aperture jitter 1.0 ps t 1 data setup time (2) 2 3.2 ns t 2 data hold time (3) 6.3 8.5 ns t d data latency 6 clocks t dr , t df data rise/fall time (4) 0.5 2 3 ns data valid (dv) duty cycle 30 40 55 % t dv input clock rising to dv fall edge 10 11.5 14 ns (1) specifications assured by design and characterization; not production tested. (2) measured from data becoming valid (at a high level = 2.0v and a low level = 0.8v) to the 50% point of the falling edge of dv. (3) measured from the 50% point of the falling edge of dv to the data becoming invalid. (4) measured between 20% to 80% of logic levels. 7 submit documentation feedback www .ti.com a n a l o g i n p u t c l k d a t a [ d 1 1 : d 0 ] d v o e d a t a d 1 1 : d 0 t o e t o e t d v t 1 t 2 t c t a n + 1 n + 2 n + 4 n + 3 n
ads5232 sbas294a ? june 2004 ? revised march 2006 timing characteristics (continued) typical values at t a = +25c, avdd = vdrv = 3.3v, sampling rate and pll state are as indicated, input clock at 50% duty cycle, and total capacitive loading = 10pf, unless otherwise noted. parameter min typ max units 50msps with pll on t a aperture delay 2.1 ns aperture jitter 1.0 ps t 1 data setup time 3.2 4.5 ns t 2 data hold time 10 11 ns t d data latency 6 clocks t dr , t df data rise/fall time 0.5 2 3 ns data valid (dv) duty cycle 30 40 55 % t dv input clock rising to dv fall edge 11.5 13.5 15.5 ns 40msps with pll on t a aperture delay 2.1 ns aperture jitter 1.0 ps t 1 data setup time 3.7 5.5 ns t 2 data hold time 11.5 13.5 ns t d data latency 6 clocks t dr , t df data rise/fall time 0.5 2 3 ns data valid (dv) duty cycle 30 40 55 % t dv input clock rising to dv fall edge 13.5 16 18.5 ns 30msps with pll off t a aperture delay 2.1 ns aperture jitter 1.0 ps t 1 data setup time 8 10 ns t 2 data hold time 14 19 ns t d data latency 6 clocks t dr , t df data rise/fall time 0.5 2 3.5 ns data valid (dv) duty cycle 30 45 55 % t dv input clock rising to dv fall edge 16 19 21 ns 20msps with pll on t a aperture delay 2.1 ns aperture jitter 1.0 ps t 1 data setup time 10 12 ns t 2 data hold time 20 25 ns t d data latency 6 clocks t dr , t df data rise/fall time 0.5 2 3.5 ns data valid (dv) duty cycle 30 45 55 % t dv input clock rising to dv fall edge 20 25 30 ns 20msps with pll off t a aperture delay 2.1 ns aperture jitter 1.0 ps t 1 data setup time 10 12 ns t 2 data hold time 20 25 ns t d data latency 6 clocks t dr , t df data rise/fall time 0.5 2 3.5 ns data valid (dv) duty cycle 30 45 55 % t dv input clock rising to dv fall edge 20 25 30 ns 2msps with pll off t a aperture delay 2.1 ns aperture jitter 1.0 ps t 1 data setup time 150 200 ns 8 submit documentation feedback www .ti.com
serial interface timing ads5232 sbas294a ? june 2004 ? revised march 2006 timing characteristics (continued) typical values at t a = +25c, avdd = vdrv = 3.3v, sampling rate and pll state are as indicated, input clock at 50% duty cycle, and total capacitive loading = 10pf, unless otherwise noted. parameter min typ max units t 2 data hold time 200 250 ns t d data latency 6 clocks t dr , t df data rise/fall time 0.5 2 3.5 ns data valid (dv) duty cycle 30 45 55 % t dv input clock rising to dv fall edge 200 225 250 ns parameter description min typ max unit t 1 serial clk period 50 ns t 2 serial clk high time 20 ns t 3 serial clk low time 20 ns t 4 data setup time 5 ns t 5 data hold time 5 ns t 6 sen fall to sclk rise 8 ns t 7 sclk rise to sen rise 8 ns 9 submit documentation feedback www .ti.com note: data is shifted in msb first. start sequence t 1 t 7 t 6 d7 (msb) d6 d5 d4 d3 d2 d1 d0 t 2 t 3 t 4 t 5 clk sen sclk sda t a outputs change on next rising clock edge after sen goes high. data latched on each rising edge of sclk.
ads5232 sbas294a ? june 2004 ? revised march 2006 serial register map: shown for the case where serial interface is used (1) address data description d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 x x x 0 normal mode 0 0 0 0 x x x 1 power-down both channels 0 0 0 0 x x 0 x straight offset binary output 0 0 0 0 x x 1 x binary two's complement output 0 0 0 0 x 0 x x channel b digital outputs enabled 0 0 0 0 x 1 x x channel b digital outputs tri-stated 0 0 0 0 0 x x x channel a digital outputs enabled 0 0 0 0 1 x x x channel a digital outputs tri-stated 0 0 1 0 0 0 0 0 normal mode 0 0 1 0 0 1 0 0 all digital outputs set to '1' 0 0 1 0 1 0 0 0 all digital outputs set to '0' 0 0 1 1 0 0 x 0 normal mode 0 0 1 1 1 x x 0 channel a powered down 0 0 1 1 x 1 x 0 channel b powered down 0 0 1 1 x x 0 0 pll enabled (default) 0 0 1 1 x x 1 0 pll disabled (1) x = don't care. 10 submit documentation feedback www .ti.com
recommended power-up sequencing ads5232 sbas294a ? june 2004 ? revised march 2006 shown for the case where the serial interface is used. power-down timing 11 submit documentation feedback s t p d d e v i c e f u l l y p o w e r s d o w n d e v i c e f u l l y p o w e r s u p 5 0 0 m s 1 m s n o t e : t h e s h o w n p o w e r ? u p t i m e i s b a s e d o n 1 m f b y p a s s c a p a c i t o r s o n t h e r e f e r e n c e p i n s . s e e t h e t h e o r y o f o p e r a t i o n s e c t i o n f o r d e t a i l s . www .ti.com t 1 t 3 t 5 t 6 t 4 t 7 t 8 t 2 a v d d ( 3 v t o 3 . 6 v ) v d r v ( 3 v t o 3 . 6 v ) d e v i c e r e a d y f o r a d c o p e r a t i o n d e v i c e r e a d y f o r a d c o p e r a t i o n d e v i c e r e a d y f o r s e r i a l r e g i s t e r w r i t e s t a r t o f c l o c k a v d d v d r v s e l s e n c l k n o t e : 1 0 m s < t 1 < 5 0 m s ; 1 0 m s < t 2 < 5 0 m s ; - 1 0 m s < t 3 < 1 0 m s ; t 4 > 1 0 m s ; t 5 > 1 0 0 n s ; t 6 > 1 0 0 n s ; t 7 > 1 0 m s ; a n d t 8 > 1 0 0 m s .
pin configuration ads5232 sbas294a ? june 2004 ? revised march 2006 pin descriptions name pin # i/o description agnd 2, 47?49, 55, 58, 59, 61, 64 analog ground avdd 3, 46, 57 analog supply clk 24 i clock input cm 52 o common-mode voltage output d0_a (lsb) 27 o data bit 12 (d0), channel a d1_a 28 o data bit 11 (d1), channel a d2_a 29 o data bit 10 (d2), channel a d3_a 30 o data bit 9 (d3), channel a d4_a 31 o data bit 8 (d4), channel a d5_a 32 o data bit 7 (d5), channel a d6_a 33 o data bit 6 (d6), channel a d7_a 34 o data bit 5 (d7), channel a d8_a 35 o data bit 4 (d8), channel a d9_a 36 o data bit 3 (d9), channel a d10_a 37 o data bit 2 (d10), channel a d11_a (msb) 38 o data bit 1 (d11), channel a d0_b (lsb) 10 o data bit 12 (d0), channel b 12 submit documentation feedback t op v iew tqfp 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 a g n d a g n d a v d d s t p d / s d a t a g n d v d r v o e a / s c l k m s b i / s e n v d r v o v r a d 1 1 _ a ( m s b ) d 1 0 _ a d 9 _ a d 8 _ a d 7 _ a d 6 _ a 12 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 s e l a g n d a v d d g n d v d r v o e b g n d v d r v o v r b d 0 _ b ( l s b ) d 1 _ b d 2 _ b d 3 _ b d 4 _ b d 5 _ b d 6 _ b a g n d i n b + i n b - a g n d i s e t a g n d a g n d a v d d i n t / e x t a g n d r e f b r e f t c m i n a - i n a + a g n d d 7 _ b d 8 _ b d 9 _ b d 1 0 _ b d 1 1 _ b ( m s b ) d v b g n d c l k g n d d v a d 0 _ a ( l s b ) d 1 _ a d 2 _ a d 3 _ a d 4 _ a d 5 _ a 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 5 3 5 2 5 1 5 0 4 9 2 8 2 9 3 0 3 1 3 2 a d s 5 2 3 2 www .ti.com
ads5232 sbas294a ? june 2004 ? revised march 2006 pin descriptions (continued) name pin # i/o description d1_b 11 o data bit 11 (d1), channel b d2_b 12 o data bit 10 (d2), channel b d3_b 13 o data bit 9 (d3), channel b d4_b 14 o data bit 8 (d4), channel b d5_b 15 o data bit 7 (d5), channel b d6_b 16 o data bit 6 (d6), channel b d7_b 17 o data bit 5 (d7), channel b d8_b 18 o data bit 4 (d8), channel b d9_b 19 o data bit 3 (d9), channel b d10_b 20 o data bit 2 (d10), channel b d11_b (msb) 21 o data bit 1 (d11), channel b dv a 26 o data valid, channel a dv b 22 o data valid, channel b gnd 4, 7, 23, 25, 44 output buffer ground in a 50 i analog input, channel a in a 51 i complementary analog input, channel a in b 63 i analog input, channel b in b 62 i complementary analog input, channel b reference select; 0 = external (default), 1 = internal; force high to set for internal reference int/ ext 56 i operation. i set 60 o bias current setting resistor of 56.2k w to ground when sel = 0, msbi (most significant bit invert) msbi/sen 41 i 1 = binary two's complement, 0 = straight offset binary (default) when sel = 1, sen (serial write enable) when sel = 0, oe a (output enable channel a) oe a /sclk 42 i 0 = enabled (default), 1 = tri-state when sel = 1, sclk (serial write clock) oe b 6 i output enable, channel b (0 = enabled [default], 1 = tri-state) ovr a 39 o over-range indicator, channel a ovr b 9 o over-range indicator, channel b ref b 54 i/o bottom reference/bypass (2 w resistor in series with a 0.1 m f capacitor to ground) ref t 53 i/o top reference/bypass (2 w resistor in series with a 0.1 m f capacitor to ground) serial interface select signal. setting sel = 0 configures pins 41, 42, and 45 as msbi, oe a , and stpd, respectively. with sel = 0, the serial interface is disabled. setting sel = 1 enables the serial interface and configures pins 41, 42, and 45 as sen, sclk, and sdata, respectively. serial sel 1 i registers can be programmed using these three signals. when used in this mode of operation, it is essential to provide a low-going pulse on sel in order to reset the serial interface registers as soon as the device is powered up. sel therefore also has the functionality of a reset signal. when sel = 0, stpd (power down) stpd/sdata 45 i 0 = normal operation (default), 1 = enabled when sel = 1, sdata (serial write data) vdrv 5, 8, 40, 43 output buffer supply 13 submit documentation feedback www .ti.com
definition of specifications minimum conversion rate analog bandwidth signal-to-noise and distortion (sinad) aperture delay aperture uncertainty (jitter) clock duty cycle signal-to-noise ratio (snr) differential nonlinearity (dnl) spurious-free dynamic range effective number of bits (enob) two-tone, third-order intermodulation integral nonlinearity (inl) maximum conversion rate ads5232 sbas294a ? june 2004 ? revised march 2006 this is the minimum sampling rate where the adc still works. the analog input frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is reduced by 3db. sinad is the ratio of the power of the fundamental (p s ) to the power of all the other spectral components including noise (p n ) and distortion (p d ), but not the delay in time between the rising edge of the input including dc. sampling clock and the actual time at which the sampling occurs. sinad is either given in units of dbc (db to carrier) the sample-to-sample variation in aperture delay. when the absolute power of the fundamental is used as the reference, or dbfs (db to full-scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. pulse width high is the minimum amount of time that the adclk pulse should be left in logic ?1? state to achieve rated performance. pulse width low is the minimum time that the adclk pulse should be left in snr is the ratio of the power of the fundamental (p s ) a low state (logic ?0?). at a given clock rate, these to the noise floor power (p n ), excluding the power at specifications define an acceptable clock duty cycle. dc and the first eight harmonics. an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation of any snr is either given in units of dbc (db to carrier) single lsb transition at the digital output from an when the absolute power of the fundamental is used ideal 1 lsb step at the analog input. if a device as the reference, or dbfs (db to full-scale) when the claims to have no missing codes, it means that all power of the fundamental is extrapolated to the possible codes (for a 12-bit converter, 4096 codes) full-scale range of the converter. are present over the full operating range. the ratio of the power of the fundamental to the the enob is a measure of converter performance as highest other spectral component (either spur or compared to the theoretical limit based on harmonic). sfdr is typically given in units of dbc (db quantization noise. to carrier). distortion two-tone imd3 is the ratio of power of the fundamental (at frequencies f 1 and f 2 ) to the power of inl is the deviation of the transfer function from a the worst spectral component of third-order reference line measured in fractions of 1 lsb using a intermodulation distortion at either frequency 2f 1 ? f 2 best straight line or best fit determined by a least or 2f 2 ? f 1 . imd3 is either given in units of dbc (db to square curve fit. inl is independent from effects of carrier) when the absolute power of the fundamental offset, gain or quantization errors. is used as the reference, or dbfs (db to full-scale) when the power of the fundamental is extrapolated to the full-scale range of the converter. the encode rate at which parametric testing is performed. this is the maximum sampling rate where certified operation is given. 14 submit documentation feedback s i n a d 1 0 l o g 1 0 p s p n p d www .ti.com s n r 1 0 l o g 1 0 p s p n e n o b s i n a d 1 . 7 6 6 . 0 2
typical characteristics ads5232 sbas294a ? june 2004 ? revised march 2006 t min = ?40c and t max = +85c. typical values are at t a = +25c, clock frequency = 65msps, 50% clock duty cycle, avdd = 3.3v, vdrv = 3.3v, transformer-coupled inputs, ?1dbfs, i set = 56.2k w , and internal voltage reference, unless otherwise noted. spectral performance spectral performance figure 1. figure 2. spectral performance spectral performance figure 3. figure 4. intermodulation distortion differential nonlinearity figure 5. figure 6. 15 submit documentation feedback a m p l i t u d e ( d b f s ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 9 . 5 2 6 6 . 5 1 3 3 2 . 5 f i n = 3 2 . 5 m h z s n r = 7 0 . 6 d b f s s i n a d = 7 0 . 4 d b f s s f d r = 8 8 . 6 d b c a m p l i t u d e ( d b f s ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 9 . 5 2 6 6 . 5 1 3 3 2 . 5 f i n = 7 0 m h z s n r = 6 7 . 7 d b f s s i n a d = 6 7 . 6 d b f s s f d r = 8 3 . 9 d b c d n l ( l s b ) c o d e 0 . 4 0 . 3 0 . 2 0 . 10 - 0 . 1 - 0 . 2 - 0 . 3 - 0 . 4 0 2 0 4 8 3 0 7 2 1 0 2 4 4 0 9 6 f i n = 5 m h z a m p l i t u d e ( d b f s ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 9 . 5 2 6 6 . 5 1 3 3 2 . 5 f 1 = 4 m h z ( - 7 d b f s ) f 2 = 5 m h z ( - 7 d b f s ) i m d = - 9 7 . 9 d b f s www .ti.com a m p l i t u d e ( d b f s ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 9 . 5 2 6 6 . 5 1 3 3 2 . 5 f i n = 1 m h z s n r = 7 1 . 4 d b f s s i n a d = 7 1 . 3 d b f s s f d r = 8 7 . 5 d b c a m p l i t u d e ( d b f s ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 9 . 5 2 6 6 . 5 1 3 3 2 . 5 f i n = 5 m h z s n r = 7 1 . 4 d b f s s i n a d = 7 1 . 3 d b f s s f d r = 8 4 . 5 d b c
ads5232 sbas294a ? june 2004 ? revised march 2006 typical characteristics (continued) t min = ?40c and t max = +85c. typical values are at t a = +25c, clock frequency = 65msps, 50% clock duty cycle, avdd = 3.3v, vdrv = 3.3v, transformer-coupled inputs, ?1dbfs, i set = 56.2k w , and internal voltage reference, unless otherwise noted. integral nonlinearity iavdd, ivdrv vs clock frequency figure 7. figure 8. dynamic performance vs clock frequency dynamic performance vs input frequency figure 9. figure 10. dynamic performance vs clock duty cycle dynamic performance vs input frequency with pll enabled (default) figure 11. figure 12. 16 submit documentation feedback i n l ( l s b ) c o d e 1 . 0 0 . 8 0 . 6 0 . 4 0 . 20 - 0 . 2 - 0 . 4 - 0 . 6 - 0 . 8 - 1 . 0 0 2 0 4 8 3 0 7 2 1 0 2 4 4 0 9 6 f i n = 5 m h z i a v d d , i d v d d ( m a ) s a m p l e r a t e ( m h z ) 0 . 1 0 0 . 0 9 0 . 0 8 0 . 0 7 0 . 0 6 0 . 0 5 0 . 0 4 0 . 0 3 0 . 0 2 0 . 0 10 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 7 0 f i n = 5 m h z i a v d d i v d r v www .ti.com snr (dbfs), sfdr (dbc) input f requency (mhz) 110100 9080 70 60 50 40 30 0 20 80 40 60 100 snr sfdr s n r , s i n a d ( d b f s ) , s f d r ( d b c ) c l o c k f r e q u e n c y ( m h z ) 9 5 9 0 8 5 8 0 7 5 7 0 6 5 6 0 5 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 6 5 7 0 s n r s f d r s i n a d f i n = 5 m h z snr (dbfs), sfdr (dbc) input f requency (mhz) 110100 9080 70 60 50 40 30 0 40 60 80 20 100 snr sfdr external reference: ref = 2v t ref = 1v b s n r ( d b f s ) , s f d r ( d b c ) d u t y c y c l e ( % ) 9 5 9 0 8 5 8 0 7 5 7 0 6 5 6 0 3 0 3 5 5 0 5 5 6 0 6 5 4 0 4 5 7 0 f i n = 5 m h z s n r s f d r
ads5232 sbas294a ? june 2004 ? revised march 2006 typical characteristics (continued) t min = ?40c and t max = +85c. typical values are at t a = +25c, clock frequency = 65msps, 50% clock duty cycle, avdd = 3.3v, vdrv = 3.3v, transformer-coupled inputs, ?1dbfs, i set = 56.2k w , and internal voltage reference, unless otherwise noted. power dissipation vs temperature dynamic performance vs temperature figure 13. figure 14. output noise swept input power figure 15. figure 16. swept input power figure 17. 17 submit documentation feedback p o w e r d i s s i p a t i o n ( m w ) t e m p e r a t u r e ( c ) 4 0 5 3 9 0 3 7 5 3 6 0 3 4 5 3 3 0 - 4 0 + 1 0 + 3 5 + 6 0 - 1 5 + 8 5 f i n = 5 m h z s n r , s f d r ( d b c ) , s n r ( d b f s ) i n p u t a m p l i t u d e ( d b f s ) 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 00 - 7 0 - 6 0 - 3 0 - 2 0 - 1 0 - 5 0 - 4 0 0 f i n = 5 m h z s n r ( d b f s ) s n r ( d b c ) s f d r ( d b c ) s a m p l e s c o d e 4 0 0 0 3 5 0 0 3 0 0 0 2 5 0 0 2 0 0 0 1 5 0 0 1 0 0 0 5 0 00 n - 5 n - 4 n - 3 n - 2 n - 1 n n + 1 n + 2 n + 3 n + 4 n + 5 s n r , s f d r ( d b c ) , s n r ( d b f s ) i n p u t a m p l i t u d e ( d b f s ) 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 00 - 7 0 - 6 0 - 3 0 - 2 0 - 1 0 - 5 0 - 4 0 0 f i n = 3 2 . 5 m h z s n r ( d b f s ) s n r ( d b c ) s f d r ( d b c ) www .ti.com s n r ( d b f s ) , s f d r ( d b c ) t e m p e r a t u r e ( c ) 9 5 9 0 8 5 8 0 7 5 7 0 6 5 6 0 5 5 - 4 0 - 1 5 + 6 0 + 1 0 + 3 5 + 8 5 f i n = 5 m h z s n r s f d r
application information theory of operation input configuration input driver configurations transformer-coupled interface ads5232 sbas294a ? june 2004 ? revised march 2006 the ads5232 is a dual-channel, simultaneous the analog input for the ads5232 consists of a sampling analog-to-digital converter (adc). its low differential sample-and-hold architecture implemented power and high sampling rate of 65msps is achieved using a switched capacitor technique; see figure 18 . using a state-of-the-art switched capacitor pipeline the sampling circuit consists of a low-pass rc filter architecture built on an advanced low-voltage cmos at the input to filter out noise components that process. the ads5232 operates from a +3.3v supply potentially could be differentially coupled on the input voltage for both its analog and digital supply pins. the inputs are sampled on two 4pf capacitors. connections. the adc core of each channel consists the rlc model is illustrated in figure 18 . of a combination of multi-bit and single-bit internal pipeline stages. each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. the conversion process is initiated by the if the application requires a signal conversion from a rising edge of the external clock. once the signal is single-ended source to drive the ads5232 captured by the input sample-and-hold amplifier, the differentially, an rf transformer could be a good input sample is sequentially converted within the solution. the selected transformer must have a pipeline stages. this process results in a data latency center tap in order to apply the common-mode dc of six clock cycles, after which the output data is voltage (v cm ) necessary to bias the converter inputs. available as a 12-bit parallel word, coded in either ac grounding the center tap will generate the straight offset binary (sob) or binary two's differential signal swing across the secondary complement (btc) format. since a common clock winding. consider a step-up transformer to take controls the timing of both channels, the analog advantage of signal amplification without the signal is sampled simultaneously. the data on the introduction of another noise source. furthermore, parallel ports is updated simultaneously as well. the reduced signal swing from the source may lead to further processing can be timed using the individual improved distortion performance. the differential data valid output signal of each channel. the input configuration may provide a noticeable ads5232 features internal references that are advantage for achieving good sfdr performance trimmed to ensure a high level of accuracy and over a wide range of input frequencies. in this mode, matching. the internal references can be disabled to both inputs (in and in) of the ads5232 see matched allow for external reference operation. impedances. figure 19 illustrates the schematic for the suggested transformer-coupled interface circuit. the component values of the rc low-pass filter may be optimized depending on the desired roll-off frequency. 18 submit documentation feedback www .ti.com
ads5232 sbas294a ? june 2004 ? revised march 2006 figure 18. input circuitry figure 19. converting a single-ended input signal into a differential signal using an rf-transformer 19 submit documentation feedback 5 n h t o 9 n h 3 . 2 p f t o 4 . 8 p f i n o u t i n p 1 . 5 p f t o 2 . 5 p f 1 w 1 5 w t o 2 5 w 5 n h t o 9 n h i n n 1 . 5 p f t o 2 . 5 p f 1 w 1 5 w t o 2 5 w 6 0 w t o 1 2 0 w 1 . 5 p f t o 1 . 9 p f i n o u t 3 . 2 p f t o 4 . 8 p f i n o u t 1 5 w t o 2 5 w 1 5 w t o 2 5 w 6 0 w t o 1 2 0 w i n o u t i n o u t 1 5 w t o 3 5 w i n o u t i n o u t o u t p o u t n s w i t c h e s t h a t a r e o n i n s a m p l e p h a s e . s w i t c h e s t h a t a r e o n i n h o l d p h a s e . v i n i n i n c m + 1 . 5 v 2 4 . 9 w 2 4 . 9 w 0 . 1 m f 2 2 p f r t 1 : n 0 . 1 m f r g r 2 r 1 o p a 6 9 0 4 9 . 9 w 1 / 2 a d s 5 2 3 2 o n e c h a n n e l o f t w o www .ti.com
dc-coupled input with differential amplifier reference circuit internal reference input over-voltage recovery ads5232 sbas294a ? june 2004 ? revised march 2006 applications that have a requirement for dc-coupling a differential amplifier, such as the ths4503, can be used to drive the ads5232; this design is shown in all bias currents required for the proper operation of figure 20 . the ths4503 amplifier easily allows a the ads5232 are set using an external resistor at i set single-ended to differential conversion, which reduces (pin 60), as shown in figure 21 . using a 56.2k w component cost. resistor on i set generates an internal reference current of about 20 m a. this current is mirrored internally to generate the bias current for the internal blocks. while a 5% resistor tolerance is adequate, deviating from this resistor value alters and degrades device performance. for example, using a larger external resistor at i set reduces the reference bias current and thereby scales down the device operating power. figure 20. using the ths4503 with the ads5232 in addition, the v ocm pin on the ths4503 can be directly tied to the common-mode pin (cm) of the ads5232 to set up the necessary bias voltage for the converter inputs. in the circuit example shown in figure 20 , the ths4503 is configured for unity gain. if required, a higher gain can easily be achieved as well by adding small capacitors (such as 10pf) in parallel with the feedback resistors to create a low-pass filter. since the ths4503 is driving a capacitive load, small figure 21. internal reference circuit series resistors in the output ensure stable operation. further details of this and the overall operation of the ths4503 may be found in its product data sheet as part of the internal reference circuit, the ads5232 (available for download at www.ti.com ). in general, provides a common-mode voltage output at pin 52, differential amplifiers provide a high-performance cm. this common-mode voltage is typically +1.5v. driver solution for baseband applications, and other while this is similar to the common-mode voltage differential amplifier models may be selected used internally within the adc pipeline core, the depending on the system requirements. cm-pin has an independent buffer amplifier, which can deliver up to 2ma of current to an external circuit for proper input signal level shifting and biasing. in order to obtain optimum dynamic the differential full-scale input range supported by the performance, the analog inputs should be biased to ads5232 is 2v pp . for a nominal value of v cm the recommended common-mode voltage (1.5v). (+1.5v), in and in can swing from 1v to 2v. the while good performance can be maintained over a ads5232 is especially designed to handle an certain cm-range, larger deviations may compromise over-voltage differential peak-to-peak voltage of 4v device performance and could also negatively affect (2.5v and 0.5v swings on in and in). if the input the overload recovery behavior. using the internal common-mode voltage is not considerably different reference mode requires the int/ ext pin to be from v cm during overload (less than 300mv), forced high, as shown in figure 21 . recovery from an over-voltage input condition is expected to be within three clock cycles. all of the the ads5232 requires solid high-frequency amplifiers in the sample-and-hold stage and the adc bypassing on both reference pins, ref t and ref b ; core are especially designed for excellent recovery see figure 21 . use ceramic 0.1 m f capacitors (size from an overload signal. 0603, or smaller), located as close as possible to the pins. 20 submit documentation feedback www .ti.com 1 m f c f c f 1 / 2 a d s 5 2 3 2 t h s 4 5 0 3 r i s o r i s o r s v s r g r t r f r f v o c m 1 0 m f 0 . 1 m f 0 . 1 m f i n i n c m r g a v d d + 5 v r e f t c m r e f b i s e t i n t / e x t a d s 5 2 3 2 0 . 1 m f 2 . 2 m f + + 2 w 2 w 5 6 k w a v d d 2 . 2 m f 0 . 1 m f
external reference (1) pll control output information clock input ads5232 sbas294a ? june 2004 ? revised march 2006 dominant in maintaining a good signal-to-noise ratio (snr). this condition is particularly critical in the ads5232 also supports the use of external if-sampling applications; for example, where the reference voltages. external reference voltage mode sampling frequency is lower than the input frequency involves applying an external top reference at ref t (under-sampling). the following equation can be used (pin 53) and a bottom reference at ref b (pin 54). to calculate the achievable snr for a given input setting the ads5232 for external reference mode frequency and clock jitter (t ja in ps rms ): also requires taking the int/ ext pin low. in this mode, the internal reference buffer is tri-stated. since the switching current for the two adc channels comes from the externally-forced references, it is the ads5232 will enter into a power-down mode if possible for the device performance to be slightly the sampling clock rate drops below a limit of lower than when the internal references are used. it approximately 2msps. if the sampling rate is should be noted that in external reference mode, v cm increased above this threshold, the ads5232 will and i set continue to be generated from the internal automatically resume normal operation. bandgap voltage, as they are in the internal reference mode. therefore, it is important to ensure that the common-mode voltage of the externally-forced reference voltages matches to within 50mv of v cm the ads5232 has an internal pll that is enabled by (+1.5v dc ). default. the pll enables a wide range of clock duty cycles. good performance is obtained for duty cycles the external reference circuit must be designed to up to 40%?60%, though the ensured electrical drive the internal reference impedance seen between specifications presume that the duty cycle is between the ref t and ref b pins. to establish the drive 45%?55%. the pll automatically limits the minimum requirements, consider that the external reference frequency of operation to 20msps. for operation circuit needs to supply an average switching current below 20msps, the pll can be disabled by of at least 1ma. this dynamic switching current programming the internal registers through the serial depends on the actual device sampling rate and the interface. with the pll disabled, the clock speed can signal level. the external reference voltages can vary go down to 2msps. with the pll disabled, the clock as long as the value of the external top reference duty cycle needs to be constrained closer to 50%. stays within the range of +1.875v to +2.0v, and the external bottom reference stays within +1.0v to +1.125v. consequently, the full-scale input range can be set between 1.5v pp and 2v pp (fsr = 2x [ref t ? the ads5232 provides two channels with 12 data ref b ] ). outputs (d11 to d0, with d11 being the msb and d0 the lsb), data-valid outputs (dv a , dv b , pin 26 and pin 22, respectively), and individual out-of-range indicator output pins (ovr a /ovr b , pin 39 and pin 9, the ads5232 requires a single-ended clock source. respectively). the clock input, clk, represents a cmos-compatible logic input with an input impedance of about 5pf. for the output circuitry of the ads5232 has been high input frequency sampling, it is recommended to designed to minimize the noise produced by use a clock source with very low jitter. a low-jitter transients of the data switching, and in particular its clock is essential in order to preserve the excellent ac coupling to the adc analog circuitry. performance of the ads5232. the converter itself is specified for a low 1.0ps (rms) jitter. generally, as the input frequency increases, clock jitter becomes more 21 submit documentation feedback www .ti.com s n r 2 0 l o g 1 0 1 2 f i n t j a
data output format (msbi) output loading output enable ( oe) serial interface over-range indicator (ovr) ads5232 sbas294a ? june 2004 ? revised march 2006 range. it will change to high if the applied signal exceeds the full-scale range. it should be noted that the ads5232 makes two data output formats each of the ovr outputs is updated along with the available: the straight offset binary code (sob) or data output corresponding to the particular sampled the binary two's complement code (btc). the analog input voltage. therefore, the ovr state is selection of the output coding is controlled by the subject to the same pipeline delay as the digital data msbi (pin 41). because the msbi pin has an internal (six clock cycles). pull-down, the ads5232 will operate with the sob code as its default setting. forcing the msbi pin high will enable btc coding. the two code structures are identical, with the exception that the msb is inverted it is recommended that the capacitive loading on the for btc format; as shown in table 1 . data output lines be kept as low as possible, preferably below 15pf. higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. such high current surges can feed digital outputs of the ads5232 can be set to back to the analog portion of the ads5232 and high-impedance (tri-state), exercising the output adversely affect device performance. if necessary, enable pins, oe a (pin 42), and oe b (pin 6). internal external buffers or latches close to the converter pull-downs configure the output in enable mode for output pins may be used to minimize the capacitive normal operation. applying a logic high voltage will loading. disable the outputs. note that the oe-function is not designed to be operated dynamically (that is, as a fast multiplexer) because it may lead to corrupt conversion results. refer to the electrical the ads5232 has a serial interface that can be used characteristics table to observe the specified tri-state to program internal registers. the serial interface is enable and disable times. disabled if sel is connected to 0. when the serial interface is to be enabled, sel serves the function of a reset signal. after the if the analog input voltage exceeds the full-scale supplies have stabilized, it is necessary to give the range set by the reference voltages, an over-range device a low-going pulse on sel. this results in all condition exists. the ads5232 incorporates a internal registers resetting to their default value of 0 function that monitors the input voltage and detects (inactive). without a reset, it is possible that registers any such out-of-range condition. this operation may be in their non-default state on power-up. this functions for each of the two channels independently. condition may cause the device to malfunction. the current state can be read at the over-range indicator pins (pins 9 and 39). this output is low when the input voltage is within the defined input table 1. coding table for differential input configuration and 2v pp full-scale input range straight offset binary (sob; msbi = 0) binary two's complement (btc; msbi = 1) differential input d11............d0 d11............d0 +fs (in = +2v, in = +1v) 1111 1111 1111 0111 1111 1111 +1/2 fs 1100 0000 0000 0100 0000 0000 bipolar zero (in = in = cmv) 1000 0000 0000 0000 0000 0000 ?1/2 fs 0100 0000 0000 1100 0000 0000 ?fs (in = +1v, in = +2v) 0000 0000 0000 1000 0000 0000 22 submit documentation feedback www .ti.com
power-down mode ads5232 sbas294a ? june 2004 ? revised march 2006 capacitances on ref t and ref b less than 1 m f, the reference voltages settle to within 1% of their the ads5232 has a power-down pin, stpd (pin 45). steady-state values in less than 500 m s. either of the the internal pull-down is in default mode for the two channels can also be selectively powered-down device during normal operation. forcing the stpd pin through the serial interface when it is enabled. high causes the device to enter into power-down mode. in power-down mode, the reference and clock the ads5232 also has an internal circuit that circuitry as well as all the channels are powered monitors the state of stopped clocks. if adclk is down. device power consumption drops to less than stopped for longer than 250ns, or if it runs at a speed 90mw. as previously mentioned, the ads5232 also less than 2mhz, this monitoring circuit generates a enters into a power-down mode if the clock speed logic signal that puts the device in a partial drops below 2msps (see the clock input section). power-down state. as a result, the power consumption of the device is reduced when clk is when stpd is pulled high, the internal buffers driving stopped. the recovery from such a partial ref t and ref b are tri-stated and the outputs are power-down takes approximately 100 m s. this forced to a voltage roughly equal to half of the constraint is described in table 2 . voltage on av dd . speed of recovery from the power-down mode depends on the value of the external capacitance on the ref t and ref b pins. for table 2. time constraints associated with device recovery from power-down and clock stoppage description typ remarks recovery from power-down mode (stpd = 1 to stpd = 0). 500 m s capacitors on ref t and ref b less than 1 m f. recovery from momentary clock stoppage ( < 250ns). 10 m s recovery from extended clock stoppage ( > 250ns). 100 m s 23 submit documentation feedback www .ti.com
layout and decoupling ads5232 sbas294a ? june 2004 ? revised march 2006 output buffer supply pins, vdrv. in order to minimize considerations the lead and trace inductance, the capacitors should be located as close to the supply pins as possible. proper grounding and bypassing, short lead length, where double-sided component mounting is allowed, and the use of ground planes are particularly they are best placed directly under the package. in important for high frequency designs. achieving addition, larger bipolar decoupling capacitors (2.2 m f optimum performance with a fast sampling converter to 10 m f), effective at lower frequencies, may also be such as the ads5232 requires careful attention to the used on the main supply pins. they can be placed on printed circuit board (pcb) layout to minimize the the pcb in proximity (< 0.5") to the adc. effects of board parasitics and to optimize component placement. a multilayer board usually ensures best if the analog inputs to the ads5232 are driven results and allows convenient component placement. differentially, it is especially important to optimize towards a highly symmetrical layout. small trace the ads5232 should be treated as an analog length differences may create phase shifts, component and the supply pins connected to clean compromising a good distortion performance. for this analog supplies. this layout ensures the most reason, the use of two single op amps rather than consistent performance results, since digital supplies one dual amplifier enables a more symmetrical layout often carry a high level of switching noise, which and a better match of parasitic capacitances. the pin could couple into the converter and degrade device orientation of the ads5232 quad-flat package follows performance. as mentioned previously, the output a flow-through design, with the analog inputs located buffer supply pins (vdrv) should also be connected on one side of the package while the digital outputs to a low-noise supply. supplies of adjacent digital are located on the opposite side. this design circuits may carry substantial current transients. the provides a good physical isolation between the supply voltage should be filtered before connecting to analog and digital connections. while designing the the vdrv pin of the converter. all ground pins should layout, it is important to keep the analog signal traces directly connect to an analog ground. separated from any digital lines to prevent noise coupling onto the analog portion. because of its high sampling frequency, the ads5232 generates high frequency current transients single-ended clock lines must be short and should and noise (clock feed-through) that are fed back into not cross any other signal traces. the supply and reference lines. if not sufficiently bypassed, this feed-through adds noise to the short circuit traces on the digital outputs will minimize conversion process. all av dd pins may be bypassed capacitive loading. trace length should be kept short with 0.1 m f ceramic chip capacitors (size 0603, or to the receiving gate (< 2") with only one cmos gate smaller). a similar approach may be used on the connected to one digital output. 24 submit documentation feedback www .ti.com
package option addendum www.ti.com 24-jan-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples ads5232ipag active tqfp pag 64 160 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr -40 to 85 ads5232ipag ADS5232IPAGG4 active tqfp pag 64 160 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr -40 to 85 ads5232ipag ads5232ipagt active tqfp pag 64 250 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr -40 to 85 ads5232ipag ads5232ipagtg4 active tqfp pag 64 250 green (rohs & no sb/br) cu nipdau level-4-260c-72 hr -40 to 85 ads5232ipag (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) only one of markings shown within the brackets will appear on the physical device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 24-jan-2013 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ads5232ipagt tqfp pag 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.0 q2 package materials information www.ti.com 26-jan-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ads5232ipagt tqfp pag 64 250 367.0 367.0 45.0 package materials information www.ti.com 26-jan-2013 pack materials-page 2
mechanical data mtqf006a january 1995 revised december 1996 post office box 655303 ? dallas, texas 75265 pag (s-pqfp-g64) plastic quad flatpack 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 4040282 / c 11/96 gage plane 33 0,17 0,27 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026

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